The present invention relates to an interface circuit for linking microprocessors by a link, which circuit ensures that the current of the link does not exceed a limit value by inserting in said link the emitter-collector path of a first transistor.
Notably in a system for reading a chip card a given number of links are established between the microprocessor on the card and the microprocessor of the card reader. Among these links, those of the "input/output" type serve to exchange data between the two microprocessors. During normal operation of the system, one of the two microprocessors transmits signals with low impedance which are received by the other microprocessor with a comparatively high impedance and the current pulses corresponding to this information remain small and, generally speaking, do not exceed a value of 2 mA.
However, it may still be that faulty operation of the system results in the two microprocessors tending to impose, with low impedance and simultaneously, opposite logic states. An excessive current then occurs in the link to the extent that one of the microprocessors is destroyed by an excessive current. The same occurs in the event of an accidental short circuit between the link and one of the power supply terminals. Notably in the case of a microchip card reading system, the microprocessor provided on the card cannot tolerate an output current in excess of approximately 10 mA. A particularly disturbing situation is that which may occur when a microchip card reader is faulty and all users presenting their card to this reader successively destroy their own card because of this fault.
The invention thus relates to an interface circuit which is intended to limit the current flowing in the link between two microprocessors so as to avoid the destruction of one of the microprocessors, and which preferably supplies a signal announcing the faulty state of the system and enabling the interruption of any other operation taking place via the link.
Generally speaking, it is known that the emitter-collector path of a transistor inserted in a link as a ballast is actually the same as the introduction of a voltage drop in said link, when the current flowing in the link exceeds a fixed limit value, under the control of a predetermined base current.
A connection in which a transistor is inserted as a ballast for feeding a load is known notably from U.S. Pat. No. 4,956,565 . However, this document offers a solution to a technical problem which deviates substantially from that envisaged by the present invention.